Prof. Pionteck

Prof. Dr.-Ing. Thilo Pionteck
Lehrstuhl Hardware-nahe Technische Informatik
Aktuelle Projekte
- Technologiegerechte 3D Verbindungsarchitekturen für heterogene, in monolithischer 3D Integration gefertigte SoCs
Laufzeit: 01.11.2022 - 31.10.2025 - ADAMANT-II: Adaptive Data Management in Evolving Heterogeneous Hardware/Software Systems
Laufzeit: 01.06.2021 - 31.05.2024 - Hybrid^2-Indexstrukturen für Hauptspeicherdatenbanken
Laufzeit: 01.01.2020 - 31.12.2023
Abgeschlossene Projekte
- Adaptives Datenmanagement für zukünftige heterogene Hardware-/Software-Systeme
Laufzeit: 01.09.2017 - 31.10.2022 - Verbundprojekt: Modulares CT-Gerät zur Diagnostik bei Kindern (KIDs-CT) - Teilvorhaben: Detektorsignalverarbeitung
Laufzeit: 01.10.2017 - 31.03.2021 - Technologiegerechte asymmetrische 3D-Verbindungsarchitekturen: Entwurfsstrategien- und methoden
Laufzeit: 01.07.2017 - 31.12.2020 - Hardwarebeschleunigung von Semantic Web Datenbanken durch dynamisch rekonfigurierbare FPGAs
Laufzeit: 01.10.2014 - 30.06.2017 - Erkennung und adaptive Priorisierung von semi-statischen Datenströmen und von Verkehrsstrommustern in Network-on-Chips
Laufzeit: 01.04.2014 - 31.12.2016
2022
Begutachteter Zeitschriftenartikel
Hardware optimizations of the X-ray pre-processing for interventional computed tomography using the FPGA
In: Applied Sciences - Basel: MDPI, Bd. 12 (2022), 11, insges. 24 S.
Buchbeitrag
Accelerated parallel hybrid GPU/CPU hash table queries with string keys
In: Konferenz: 33rd International Conference on Database and Expert Systems Applications, DEXA 2022, Vienna, Austria, August 22-24, 2022, Database and Expert Systems Applications - Cham: Springer International Publishing; Strauss, Christine . - 2022, S. 191-203 - (Lecture notes in computer science; volume 13427)
Dead-ends in FPGAs for database acceleration
In: Konferenz: 21st International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2021, virtual event, July 4-8, 2021, Embedded Computer Systems: Architectures, Modeling, and Simulation - Cham: Springer International Publishing; Orailoglu, Alex . - 2022, S. 493-504 - (Lecture notes in computer science; volume 13227)
Hardware isolation support for low-cost SoC-FPGAs
In: Konferenz: International Conference on Architecture of Computing Systems, ARCS 2022, Heilbronn, Germany, September 13-15, 2022, Architecture of computing systems - 35th International Conference, ARCS 2022, Heilbronn, Germany, September 13-15, 2022 : proceedings - Cham: Springer; Schulz, Martin . - 2022, S. 148-163 - (Lecture notes in computer science; volume 13642)
Herausgeberschaft
Architecture of computing systems - 35th International Conference, ARCS 2022, Heilbronn, Germany, September 13-15, 2022 : proceedings
In: Cham: Springer, 2022, 1 Online-Ressource - (Lecture notes in computer science; volume 13642)
Wissenschaftliche Monographie
3D Interconnect Architectures for Heterogeneous Technologies - Modeling and Optimization
In: Cham: Imprint: Springer, 2022., 1st ed. 2022., 1 Online-Ressource(XXV, 395 p. 102 illus., 100 illus. in color.) - (Springer eBook Collection)
2021
Begutachteter Zeitschriftenartikel
In-depth analysis of OLAP query performance on heterogeneous hardware
In: Datenbank-Spektrum - Berlin: Springer, Bd. 21 (2021), S. 133-143
Ratatoskr - an open-source framework for in-depth power, performance, and area analysis and optimization in 3D NoCs
In: ACM transactions on modeling and computer simulation/ Association for Computing Machinery - New York, NY: ACM Press, Bd. 32 (2021), 1, insges. 21 S.
Buchbeitrag
An investigation of atomic synchronization for sort-based group-by aggregation on GPUs
In: 2021 IEEE 37th International Conference on Data Engineering workshops/ IEEE International Conference on Data Engineering - Piscataway, NJ: IEEE . - 2021, S. 48-53
Architecture, dataflow and physical design implications of 3D-ICs for DNN-accelerators
In: Proceedings of the Twenty Second International Symposium on Quality Electronic Design/ ISQED - [Piscataway, NJ]: IEEE; Ghosh, Swaroop . - 2021, S. 60-66
Bridging the frequency gap in heterogeneous 3D SoCs through technology-specific NoC router architectures
In: Proceedings of the 26th Asia and South Pacific Design Automation Conference - New York,NY,United States: Association for Computing Machinery . - 2021, S. 197-203
Configurable pipelined datapath for data acquisition in interventional computed tomography
In: 29th IEEE International Symposium on Field-Programmable Custom Computing Machines/ IEEE International Symposium on Field-Programmable Custom Computing Machines - Piscataway, NJ: IEEE; Bobda, Christophe . - 2021, S. 257
CuART - a CUDA-based, scalable Radix-Tree lookup and update engine
In: Konferenz: 50th International Conference on Parallel Processing, ICPP 2021, Lemont, Il, USA, August 9 - 12, 2021, 50th International Conference on Parallel Processing - New York,NY,United States: Association for Computing Machinery . - 2021, insges. 10 S.
StreamGrid - an AXI-stream-compliant overlay architecture
In: Symposium: 17th International Symposium, ARC 2021, Virtual Event, June 2930, 2021, Applied Reconfigurable Computing. Architectures, Tools, and Applications/ ARC - Cham: Springer International Publishing; Derrien, Steven . - 2021, S. 156-170 - ( Lecture notes in computer science; volume 12700)
Ultra-low-latency video encoding on heterogenous hardware platforms
In: 2020 International Conference on Field-Programmable Technology - Piscataway, NJ: IEEE . - 2021, S. 287
Herausgeberschaft
Architecture of Computing Systems - 34th International Conference, ARCS 2021, Virtual Event, June 78, 2021, Proceedings
In: Cham: Imprint: Springer, 2021., 1st ed. 2021., 1 Online-Ressource(XVIII, 229 p. 81 illus., 67 illus. in color.) - (Springer eBook Collection; Theoretical Computer Science and General Issues; 12800)
2020
Artikel in Kongressband
When vectorwise meets hyper, pipeline breakers become the moderator
In: ADMS 2020: eleventh International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures : Monday, August 31, 2020 : in conjunction with VLDB 2020 - Tokyo . - 2020
Begutachteter Zeitschriftenartikel
Application-specific SoC design using core mapping to 3D mesh NoCs with nonlinear area optimization and simulated annealing
In: Technologies: open access journal - Basel: MDPI, Bd. 8 (2020), 1, insges. 10 S.
Buchbeitrag
Hardware/Software Co-Design of a control and data acquisition system for Computed Tomography
In: 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST)/ MOCAST - [Piscataway, NJ]: IEEE . - 2020, insges. 4 S.
He..ro DB - a concept for parallel data processing on heterogeneous hardware
In: Architecture of Computing Systems ARCS 2020 - 33rd International Conference, Aachen, Germany, May 2528, 2020, Proceedings: 33rd International Conference, Aachen, Germany, May 2528, 2020, Proceedings - Cham: Springer International Publishing; Brinkmann, André. . - 2020, S. 82-96 - ( Lecture notes in computer science; 12155)
Optimising operator sets for analytical database processing on FPGAs
In: Applied Reconfigurable Computing. Architectures, Tools, and Applications: 16th International Symposium, ARC 2020, Toledo, Spain, April 13, 2020, Proceedings - Cham: Springer International Publishing . - 2020, S. 30-44 - (Lecture Notes in Computer Science; volume 12083)
Parallelizing approximate search on adaptive radix trees
In: CEUR workshop proceedings - Aachen, Germany: RWTH Aachen, Bd. 2646 (2020), S. 56-67
Ultra-low-latency video encoding on heterogenous hardware platforms
In: 2020 International Conference on Field-Programmable Technology/ International Conference on Field-Programmable Technology - Piscataway, NJ: IEEE; Lin, Mingjie . - 2020, S. 287
Herausgeberschaft
Architecture of Computing Systems ARCS 2020 - 33rd International Conference, Aachen, Germany, May 2528, 2020, Proceedings
In: Cham: Imprint: Springer, 2020., 1st ed. 2020., 1 Online-Ressource(XII, 257 p. 112 illus., 62 illus. in color.) - (Springer eBook Collection; Theoretical Computer Science and General Issues; 12155)
2019
Abstract
Computed tomography hardware architectural model FPGA-based
In: 4th Image-Guided Interventions Conference: digitalization in medicine : November 4th-5th 2019, UMM, Mannheim - Mannheim, 2019 . - 2019
Begutachteter Zeitschriftenartikel
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment
In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, 1983, Bd. 67.2019, S. 60-72
NoCs in heterogeneous 3D SoCs - co-design of routing strategies and microarchitectures
In: IEEE access/ Institute of Electrical and Electronics Engineers - New York, NY: IEEE, Bd. 7 (2019), S. 135145-135163
Simulation environment for link energy estimation in networks-on-chip with virtual channels
In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, 1983 . - 2019
Buchbeitrag
Area optimization with non-linear models in core mapping for system-on-chips
In: 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST): May 13-15, 2019, Aristotle University Research Dissemination Center (KEDEA), Thessaloniki, Greece/ International Conference on Modern Circuits and Systems Technologies - [Piscataway, NJ]: IEEE . - 2019
Efficient inter-kernel communication for OpenCL database operators on FPGAs
In: 2018 International Conference on Field-Programmable Technology (FPT) - [Piscataway, NJ]: IEEE, 2019
Hardware-accelerated index construction for semantic web
In: Konferenz: 2018 International Conference on Field-Programmable Technology, FPT, Naha, Okinawa, Japan, 10-14 December 2018, 2018 International Conference on Field-Programmable Technology/ International Conference on Field-Programmable Technology - Piscataway, NJ: IEEE . - 2019
Survey on FPGAs in medical radiology applications - challenges, architectures and programming models
In: Konferenz: International Conference on Field-Programmable Technology, ICFPT, Tianjin, China, 09-13 December 2019, 2019 International Conference on Field-Programmable Technology/ ICFPT - Piscataway, NJ: IEEE . - 2019, S. 279-282
System-level optimization of network-on-chips for heterogeneous 3D system-on-chips
In: Konferenz: IEEE 37th International Conference on Computer Design, ICCD, Abu Dhabi, United Arab Emirates, 17-20 November 2019, 2019 IEEE International Conference on Computer Design/ IEEE International Conference on Computer Design - Piscataway, NJ: IEEE . - 2019, S. 409-412
Dissertation
Networks-on-Chip for heterogeneous 3D Systems-on-Chip
In: Magdeburg, 2019, xiv, 248 Seiten, Illustrationen, Diagramme, 30 cm ; [Literaturverzeichnis: Seite 235-246]
Herausgeberschaft
ARCS 2019 - 32nd GI/ITG International Conference on Architecture of Computing Systems : workshop proceedings : May 20-21, 2019, Technical University of Denmark, Copenhagen, Denmark
In: Berlin: VDE Verlag, 2019, 1 CD-ROM, 56 g ; Kongress: GI/ITG International Conference on Architecture of Computing Systems 32 : Copenhagen$d2019.05.20-21
Architecture of Computing Systems ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 2023, 2019, Proceedings
In: Cham: Springer, 2019, 1 Online-Ressource (XIX, 335 p. 212 illus., 88 illus. in color) - (Springer eBooks; Computer Science; Theoretical Computer Science and General Issues; 11479)
2018
Begutachteter Zeitschriftenartikel
Cooking DBMS operations using granular primitives - an overview on a primitive-based RDBMS query evaluation
In: Datenbank-Spektrum - Berlin: Springer, Bd. 18.2018, 3, S. 183-193
Hardware-aided update acceleration in a hybrid Semantic Web database system
In: The journal of supercomputing: an international journal of high-performance computer design, analysis and use - Dordrecht [u.a.]: Springer Science + Business Media B.V, insges. 24 S., 2018
Integration of FPGAs in database management systems - challenges and opportunities
In: Datenbank-Spektrum - Berlin: Springer, Bd. 18.2018, 3, S. 145-156
Buchbeitrag
Adaptive data processing in heterogeneous hardware systems
In: CEUR workshop proceedings - Aachen: RWTH, Bd. 2126.2018, S. 10-15 ; [Workshop: 30th GI-Workshop Grundlagen von Datenbanken, Wuppertal, Germany, May 22-25, 2018]
An FPGA-based prototyping framework for Networks-on-Chip
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 7 S., 2018
Coding-aware link energy estimation for 2D and 3D networks-on-chip with virtual channels
In: 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018): 2-4 July 2018, Spain/ IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation - Piscataway, NJ: IEEE, 2018; IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (28.:2018) . - 2018, S. 222-228
Continuous live-tracing as debugging approach on FPGAs
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018
Search & update optimization of a B + tree in a hardware aided semantic web database system
In: Proceedings of the 7th International Conference on Emerging Databases - Singapore: Springer, S. 172-182, 2018 - (Lecture Notes in Electrical Engineering; 461)
Specification of simulation models for NoCs in heterogeneous 3D SoCs
In: Proceedings of the 13th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC): July 9th-11th, 2018, Lille, France - Piscataway, NJ: IEEE, insges. 8 S.
Herausgeberschaft
ARCS 2018 - 31th International Conference on Architecture of Computing Systems April, 9-12, 2018, Technische Universität Braunschweig, Braunschweig, Germany, Workshop Proceedings
In: Berlin: VDE Verlag, 2018, CD-ROM, 12 cm ; Kongress: GI/ITG International Conference on Architecture of Computing Systems 31 (Braunschweig : 2018.04.09-12)
Architecture of Computing Systems ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 912, 2018, Proceedings
In: Cham: Springer, 2018, Online-Ressource (XV, 326 p. 112 illus, online resource) - (Springer eBook Collection; Computer Science; SpringerLink; Bücher; Lecture Notes in Computer Science; 10793)
2017
Begutachteter Zeitschriftenartikel
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs$Jan Moritz Joseph, ChristopherBlochwitz, Alberto García-Ortiz, Thilo Piontecka
In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, 1979, Bd. 48.2017, S. 36-47
Semi-static operator graphs for accelerated query execution on FPGAs
In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, 2017
Buchbeitrag
An FPGA-based prototyping framework for networks-on-Chip
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; poster session A]
Contentious live-tracing as debugging approach on FPGAS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; General session]
Design method for asymmetric 3D interconnect architectures with high level models
In: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017): July 12-14, 2017, Madrid, Spain : proceedings - [Piscataway, NJ]: IEEE, insges. 8 S.
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; Poster session B]
Hardware-accelerated radix-tree based string sorting for big data applications
In: Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 36, 2017, Proceedings - Cham: Springer, 2017 . - 2017, S. 47-58 - (Lecture Notes in Computer Science; 10172)
Herausgeberschaft
ARCS 2017 - 30th International Conference on Architecture of Computing Systems : workshop proceedings : April, 3-6, 2017, Vienna University of Technology, Vienna, Austria
In: Berlin Offenbach VDE Verlag GmbH [2017], 1 CD-ROM, ISBN 978-3-8007-4395-7 ; Kongress: ARCS 30 (Wien : 2017)
Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 36, 2017, Proceedings
In: Cham: Springer, 2017, Online-Ressource (XIII, 262 p. 100 illus, online resource) - (Springer eBook Collection; Computer Science; SpringerLink; Bücher; Lecture Notes in Computer Science; 10172)
2016
Begutachteter Zeitschriftenartikel
Runtime adaptive hybrid query engine based on FPGAs
In: Open journal of databases: OJDB - Lübeck: RonPub UG, Bd. 3.2016, 1, S. 21-41
Buchbeitrag
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
In: 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc): June 27-29, 2016, Tallinn, Estonia - [Piscataway, NJ]: IEEE
Accelerated join evaluation in Semantic Web databases by using FPGAs
In: Concurrency Computation, Vol. 28, 2016, Issue 7, S. 2031-2051, 10.1002/cpe.3502
Adaptive allocation of default router paths in Network-on-Chips for latency reduction
In: Proceedings of the 2016 International Conference on High Performance Computing & Simulation (HPCS 2016): July 18-22, 2016, Innsbruck, Austria - Piscataway, NJ: IEEE
An architectural template for composing application specific datapaths at runtime
In: 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2016, 10.1109/ReConFig.2015.7393300
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases
In: 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2016, 10.1109/ReConFig.2015.7393291
Hardware-accelerated pose estimation for embedded systems using vivado HLS
In: ReConFig: 2016 International Conference on Reconfigurable Computing and FPGAs : November 30 - December 2, Cancun, Mexico - Piscataway, NJ: IEEE ; [Kongress: 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig, Cancun, Mexico, November 30 - December 2, 2016]
Herausgeberschaft
Architecture of Computing Systems – ARCS 2016
In: Vol. Architecture of Computing Systems ARCS 2016, 2016, S. , ISSN 0302-9743, 10.1007/978-3-319-30695-7
2015
Begutachteter Zeitschriftenartikel
RAW 2014: Random number generators on FPGAS
In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 9, 2015, Issue 2, 10.1145/2807699
Buchbeitrag
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
In: 2015 Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP and International Symposium on System-on-Chip, SoC 2015, 2015, 10.1109/NORCHIP.2015.7364370
Automated composition and execution of hardware-Accelerated operator graphs
In: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015, 2015, 10.1109/ReCoSoC.2015.7238078
Hybrid FPGA approach for a B+ tree in a Semantic Web database system
In: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015, 2015, 10.1109/ReCoSoC.2015.7238093
2014
Buchbeitrag
A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling
In: 2014 International Symposium on System-on-Chip, SoC 2014, 2014, 10.1109/ISSOC.2014.6972440
Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation
In: 2014 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2014, 2014, 10.1109/ReConFig.2014.7032533
Influence of magnetic fields and X-radiation on ring oscillators in FPGAs
In: Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS, 2014, S. 199-204, 10.1109/IPDPSW.2014.26
Parallel and pipelined filter operator for hardware-accelerated operator graphs in semantic web databases
In: Proceedings - 2014 IEEE International Conference on Computer and Information Technology, CIT 2014, 2014, S. 539-546, 10.1109/CIT.2014.162
2013
Buchbeitrag
Hardware-accelerated join processing in large Semantic Web databases with FPGAs
In: Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013, 2013, S. 131-138, 10.1109/HPCSim.2013.6641403
Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems
In: Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013, 2013, S. 229-232, 10.1109/HPCSim.2013.6641419
Register allocation for high-level synthesis of hardware accelerators targeting FPGAs
In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, 2013, 10.1109/ReCoSoC.2013.6581522
2012
Buchbeitrag
An approach for performance estimation of hybrid systems with FPGAs and GPUs as coprocessors
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 7179 LNCS, 2012, S. 160-171, 10.1007/978-3-642-28293-5_14
2011
Buchbeitrag
Linking formal description and simulation of runtime reconfigurable systems
In: Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, 2011, S. 158-163, 10.1109/ReConFig.2011.55
2010
Buchbeitrag
A concept of a trust management architecture to increase the robustness of nano age devices
In: Proceedings of the International Conference on Dependable Systems and Networks, 2010, S. 142-147, 10.1109/DSNW.2010.5542604
Latency reduction of selected data streams in network-on-chips for adaptive manycore systems
In: 28th Norchip Conference, NORCHIP 2010, 2010, 10.1109/NORCHIP.2010.5669432
Optimizing runtime reconfiguration decisions
In: Proceedings - IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2010, 2010, S. 39-46, 10.1109/EUC.2010.16
Herausgeberschaft
DynaCORE-dynamically reconfigurable coprocessor for network processors
In: Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, 2010, S. 335-354, 10.1007/978-90-481-3485-4_16
2009
Buchbeitrag
On the impact of buffer size on packet loss in adaptable network-on-chips for runtime reconfigurable system-on-chips
In: 2009 NORCHIP, 2009, 10.1109/NORCHP.2009.5397798
2008
Begutachteter Zeitschriftenartikel
Adaptive communication architectures for runtime reconfigurable system-on-chips
In: Parallel Processing Letters, Vol. 18, 2008, Issue 2, S. 275-289, 10.1142/S0129626408003387
Buchbeitrag
An application-oriented synthetic network traffic generator
In: Proceedings - 22nd European Conference on Modelling and Simulation, ECMS 2008, 2008, S. 299-305
Design and simulation of runtime reconfigurable systems
In: Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, 2008, S. 154-157, 10.1109/DDECS.2008.4538776
On the design parameters of runtime reconfigurable systems
In: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008, S. 683-686, 10.1109/FPL.2008.4630039
Performance analysis of bus-based interconnects for a run-time reconfigurable co-processor platform
In: Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2008, 2008, S. 200-205, 10.1109/PDP.2008.52
SPP1148 booth: Network processors
In: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008, S. 352, 10.1109/FPL.2008.4629960
WCET determination tool for embedded systems software
In: SIMUTools 2008 - 1st International ICST Conference on Simulation Tools and Techniques for Communications, Networks and Systems, 2008, 10.4108/ICST.SIMUTOOLS2008.3044
2007
Buchbeitrag
A lightweight framework for runtime reconfigurable system prototyping
In: Proceedings of the International Workshop on Rapid System Prototyping, 2007, S. 61-64, 10.1109/RSP.2007.7
Communication architectures for dynamically reconfigurable FPGA designs
In: Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM, 2007, 10.1109/IPDPS.2007.370364
Modelling tile-based run-time reconfigurable systems using SystemC
In: 21st European Conference on Modelling and Simulation: Simulations in United Europe, ECMS 2007, 2007, S. 509-514
On the design of a dynamically reconfigurable function-unit for error detection and correction
In: IFIP International Federation for Information Processing, Vol. 240, 2007, S. 283-297, 10.1007/978-0-387-73661-7_18
Teaching informatics students the secrets of hardware design
In: Proceedings - MSE 2007: 2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World, 2007, S. 31-32, 10.1109/MSE.2007.82
2006
Begutachteter Zeitschriftenartikel
Exploring the capabilities of reconfigurable hardware for OFDM-based wlans
In: IFIP International Federation for Information Processing, Vol. 200, 2006, S. 149-164, 10.1007/0-387-33403-3_10
Buchbeitrag
A dynamically reconfigurable packet-switched network-on-chip
In: Proceedings -Design, Automation and Test in Europe, DATE, Vol. 1, 2006
An adaptive system-on-chip for network applications
In: 20th International Parallel and Distributed Processing Symposium, IPDPS 2006, Vol. 2006, 2006, 10.1109/IPDPS.2006.1639445
Applying partial reconfiguration to networks-on-chips
In: Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, 2006, S. 155-160, 10.1109/FPL.2006.311208
2005
Buchbeitrag
Reconfigurable embedded systems: An application-oriented perspective on architectures and design techniques
In: Lecture Notes in Computer Science, Vol. 3553, 2005, S. 12-21
2004
Buchbeitrag
A dynamically reconfigurable function-unit for error detection and correction in mobile terminals
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 3203, 2004, S. 1090-1092
Design of a reconfigurable AES encryption/decryption engine for mobile terminals
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 2004, S. II545-II548
Reconfigurable platforms for ubiquitous computing
In: 2004 Computing Frontiers Conference, 2004, S. 377-389
2003
Begutachteter Zeitschriftenartikel
On the Rapid Prototyping of Equalizers for OFDM Systems
In: Design Automation for Embedded Systems, Vol. 8, 2003, Issue 4, S. 283-295, 10.1023/B:DAEM.0000013063.88613.e0
Buchbeitrag
Hardware evaluation of low power communication mechanisms for transport-triggered architectures
In: Proceedings of the International Workshop on Rapid System Prototyping, Vol. 2003-January, 2003, S. 141-147, 10.1109/IWRSP.2003.1207041
Reconfiguration requirements for high speed wireless communication systems
In: Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003, 2003, S. 118-125, 10.1109/FPT.2003.1275739
2002
Buchbeitrag
A framework for teaching (re)configurable architectures in student projects
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2438 LNCS, 2002, S. 444-451
On the rapid prototyping of equalizers for OFDM systems
In: Proceedings of the International Workshop on Rapid System Prototyping, Vol. 2002-January, 2002, S. 48-52, 10.1109/IWRSP.2002.1029737
2001
Buchbeitrag
Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture
In: Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001, 2001, S. 41-46, 10.1109/IWV.2001.923138
Efficient mapping of pre-synthesized IP-cores onto dynamically reconfigurable array architectures
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2147, 2001, S. 584-589
On the numerical accuracy of cordic-based frequency offset compensation in burst oriented OFDM systems
In: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Vol. 2, 2001, S. 1069-1072
Herausgeberschaft
Effiziente IP-basierte abbildungsverfahren für dynamisch rekonfigurierbare array-architekturen
In: ITG-Fachbericht, 2001, Issue 164, S. 315
2000
Buchbeitrag
An application-tailored dynamically reconfigurable hardware architecture for digital baseband processing
In: Proceedings - 13th Symposium on Integrated Circuits and Systems Design, 2000, S. 341-346, 10.1109/SBCCI.2000.876052
DReAM: A dynamically reconfigurable architecture for future mobile communication applications
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 1896, 2000, S. 312-321
- Privatdozent Dr. Sven Groppe, Universität zu Lübeck
- Otto-von-Guericke-Univeristät Magdeburg, Prof. Gunter Saake
- Universität zu Lübeck, Institut für Informationssysteme
- Georgia Tech, School of Electrical and Computer Engineering, Atlanta
- Universität Bremen, Prof. Alberto Garcia-Ortiz
- Entwurfsraumexploration für kombinierte Hardware-/Softwaresysteme
- Entwurf und FPGA-Prototyping digitaler Schaltungen