Application-specific SoC design using core mapping to 3D mesh NoCs with nonlinear area optimization and simulated annealing
In: Technologies: open access journal - Basel: MDPI, 2013, Bd. 8.2020, 1, insges. 10 S.

Optimising operator sets for analytical database processing on FPGAs
In: Applied Reconfigurable Computing. Architectures, Tools, and Applications: 16th International Symposium, ARC 2020, Toledo, Spain, April 13, 2020, Proceedings - Cham: Springer International Publishing, 2020; Rincón, Fernando . - 2020, S. 30-44 - (Lecture Notes in Computer Science; volume12083)

Computed tomography hardware architectural model FPGA-based
In: 4th Image-Guided Interventions Conference: digitalization in medicine : November 4th-5th 2019, UMM, Mannheim - Mannheim, 2019 . - 2019 ; [Konferenz: 4th Image-Guided Interventions Conference, Mannheim, Germany, November 4 - 5, 2019]

Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment
In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, Bd. 67.2019, S. 60-72

NoCs in heterogeneous 3D SoCs - co-design of routing strategies and microarchitectures
In: IEEE access - New York, NY: IEEE, Bd. 7.2019, S. 135145-135163

Simulation environment for link energy estimation in networks-on-chip with virtual channels
In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, 2019

Area optimization with non-linear models in core mapping for system-on-chips
In: 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST) - [Piscataway, NJ]: IEEE

Efficient inter-kernel communication for OpenCL database operators on FPGAs
In: 2018 International Conference on Field-Programmable Technology (FPT) - [Piscataway, NJ]: IEEE, 2019

Hardware-accelerated index construction for semantic web
In: 2018 International Conference on Field-Programmable Technology (FPT) - [Piscataway, NJ]: IEEE, 2019

Networks-on-Chip for heterogeneous 3D Systems-on-Chip
In: Magdeburg, 2019, xiv, 248 Seiten, Illustrationen, Diagramme, 30 cm ; [Literaturverzeichnis: Seite 235-246]

ARCS 2019 - 32nd GI/ITG International Conference on Architecture of Computing Systems : workshop proceedings : May 20-21, 2019, Technical University of Denmark, Copenhagen, Denmark
In: Berlin: VDE Verlag, 2019, 1 CD-ROM, 56 g ; Kongress: GI/ITG International Conference on Architecture of Computing Systems 32 : Copenhagen$d2019.05.20-21

Architecture of Computing Systems ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 2023, 2019, Proceedings
In: Cham: Springer, 2019, 1 Online-Ressource (XIX, 335 p. 212 illus., 88 illus. in color) - (Springer eBooks; Computer Science; Theoretical Computer Science and General Issues; 11479)

Cooking DBMS operations using granular primitives - an overview on a primitive-based RDBMS query evaluation
In: Datenbank-Spektrum - Berlin: Springer, Bd. 18.2018, 3, S. 183-193

Hardware-aided update acceleration in a hybrid Semantic Web database system
In: The journal of supercomputing: an international journal of high-performance computer design, analysis and use - Dordrecht [u.a.]: Springer Science + Business Media B.V, insges. 24 S., 2018

Integration of FPGAs in database management systems - challenges and opportunities
In: Datenbank-Spektrum - Berlin: Springer, Bd. 18.2018, 3, S. 145-156

Adaptive data processing in heterogeneous hardware systems
In: CEUR workshop proceedings - Aachen: RWTH, Bd. 2126.2018, S. 10-15 ; [Workshop: 30th GI-Workshop Grundlagen von Datenbanken, Wuppertal, Germany, May 22-25, 2018]

An FPGA-based prototyping framework for Networks-on-Chip
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 7 S., 2018

Coding-aware link energy estimation for 2D and 3D networks-on-chip with virtual channels
In: 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018): 2-4 July 2018, Spain - Piscataway, NJ: IEEE, S. 222-228

Continuous live-tracing as debugging approach on FPGAs
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018

Search & update optimization of a B + tree in a hardware aided semantic web database system
In: Proceedings of the 7th International Conference on Emerging Databases - Singapore: Springer, S. 172-182, 2018 - (Lecture Notes in Electrical Engineering; 461)

Specification of simulation models for NoCs in heterogeneous 3D SoCs
In: Proceedings of the 13th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC): July 9th-11th, 2018, Lille, France - Piscataway, NJ: IEEE, insges. 8 S.

ARCS 2018 - 31th International Conference on Architecture of Computing Systems April, 9-12, 2018, Technische Universität Braunschweig, Braunschweig, Germany, Workshop Proceedings
In: Berlin: VDE Verlag, 2018, CD-ROM, 12 cm ; Kongress: GI/ITG International Conference on Architecture of Computing Systems 31 (Braunschweig : 2018.04.09-12)

Architecture of Computing Systems ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 912, 2018, Proceedings
In: Cham: Springer, 2018, Online-Ressource (XV, 326 p. 112 illus, online resource) - (Springer eBook Collection; Computer Science; SpringerLink; Bücher; Lecture Notes in Computer Science; 10793)

Architecture of Computing Systems - ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 9-12, 2018, Proceedings
In: Cham: Springer International Publishing, 2018, 1 Online-Ressource (XV, 326 p. 112 illus) - (Lecture Notes in Computer Science; 10793)

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs$Jan Moritz Joseph, ChristopherBlochwitz, Alberto García-Ortiz, Thilo Piontecka
In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, Bd. 48.2017, S. 36-47

Semi-static operator graphs for accelerated query execution on FPGAs
In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, 2017

An FPGA-based prototyping framework for networks-on-Chip
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; poster session A]

Contentious live-tracing as debugging approach on FPGAS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; General session]

Design method for asymmetric 3D interconnect architectures with high level models
In: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017): July 12-14, 2017, Madrid, Spain : proceedings - [Piscataway, NJ]: IEEE, insges. 8 S.

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
In: ReConFig\'17: 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ: IEEE ; [Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig\'17, Cancun, Mexico, December 4-6, 2017; Poster session B]

Hardware-accelerated radix-tree based string sorting for big data applications
In: Architecture of Computing Systems - ARCS 2017 - Cham: Springer, S. 47-58 - (Lecture Notes in Computer Science; 10172)

ARCS 2017 - 30th International Conference on Architecture of Computing Systems : workshop proceedings : April, 3-6, 2017, Vienna University of Technology, Vienna, Austria
In: Berlin Offenbach VDE Verlag GmbH [2017], 1 CD-ROM, ISBN 978-3-8007-4395-7 ; Kongress: ARCS 30 (Wien : 2017)

Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 3-6, 2017, Proceedings
In: s.l., Imprint: Springer, 2017, 1 Online-Ressource (XIII, 262 p. 100 illus) - (Lecture Notes in Computer Science; 10172)

Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 36, 2017, Proceedings
In: Cham: Springer, 2017, Online-Ressource (XIII, 262 p. 100 illus, online resource) - (Springer eBook Collection; Computer Science; SpringerLink; Bücher; Lecture Notes in Computer Science; 10172)

Runtime adaptive hybrid query engine based on FPGAs
In: Open journal of databases: OJDB - Lübeck: RonPub UG, Bd. 3.2016, 1, S. 21-41

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
In: 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc): June 27-29, 2016, Tallinn, Estonia - [Piscataway, NJ]: IEEE

Accelerated join evaluation in Semantic Web databases by using FPGAs
In: Concurrency Computation, Vol. 28, 2016, Issue 7, S. 2031-2051, 10.1002/cpe.3502

Adaptive allocation of default router paths in Network-on-Chips for latency reduction
In: Proceedings of the 2016 International Conference on High Performance Computing & Simulation (HPCS 2016): July 18-22, 2016, Innsbruck, Austria - Piscataway, NJ: IEEE

An architectural template for composing application specific datapaths at runtime
In: 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2016, 10.1109/ReConFig.2015.7393300

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases
In: 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2016, 10.1109/ReConFig.2015.7393291

Hardware-accelerated pose estimation for embedded systems using vivado HLS
In: ReConFig: 2016 International Conference on Reconfigurable Computing and FPGAs : November 30 - December 2, Cancun, Mexico - Piscataway, NJ: IEEE ; [Kongress: 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig, Cancun, Mexico, November 30 - December 2, 2016]

Architecture of Computing Systems – ARCS 2016
In: Vol. Architecture of Computing Systems ⿿ ARCS 2016, 2016, S. , ISSN 0302-9743, 10.1007/978-3-319-30695-7

RAW 2014: Random number generators on FPGAS
In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 9, 2015, Issue 2, 10.1145/2807699

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
In: 2015 Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP and International Symposium on System-on-Chip, SoC 2015, 2015, 10.1109/NORCHIP.2015.7364370

Automated composition and execution of hardware-Accelerated operator graphs
In: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015, 2015, 10.1109/ReCoSoC.2015.7238078

Hybrid FPGA approach for a B+ tree in a Semantic Web database system
In: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015, 2015, 10.1109/ReCoSoC.2015.7238093

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling
In: 2014 International Symposium on System-on-Chip, SoC 2014, 2014, 10.1109/ISSOC.2014.6972440

Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation
In: 2014 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2014, 2014, 10.1109/ReConFig.2014.7032533

Influence of magnetic fields and X-radiation on ring oscillators in FPGAs
In: Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS, 2014, S. 199-204, 10.1109/IPDPSW.2014.26

Parallel and pipelined filter operator for hardware-accelerated operator graphs in semantic web databases
In: Proceedings - 2014 IEEE International Conference on Computer and Information Technology, CIT 2014, 2014, S. 539-546, 10.1109/CIT.2014.162

Hardware-accelerated join processing in large Semantic Web databases with FPGAs
In: Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013, 2013, S. 131-138, 10.1109/HPCSim.2013.6641403

Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems
In: Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013, 2013, S. 229-232, 10.1109/HPCSim.2013.6641419

Register allocation for high-level synthesis of hardware accelerators targeting FPGAs
In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, 2013, 10.1109/ReCoSoC.2013.6581522

An approach for performance estimation of hybrid systems with FPGAs and GPUs as coprocessors
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 7179 LNCS, 2012, S. 160-171, 10.1007/978-3-642-28293-5_14

Linking formal description and simulation of runtime reconfigurable systems
In: Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, 2011, S. 158-163, 10.1109/ReConFig.2011.55

A concept of a trust management architecture to increase the robustness of nano age devices
In: Proceedings of the International Conference on Dependable Systems and Networks, 2010, S. 142-147, 10.1109/DSNW.2010.5542604

Latency reduction of selected data streams in network-on-chips for adaptive manycore systems
In: 28th Norchip Conference, NORCHIP 2010, 2010, 10.1109/NORCHIP.2010.5669432

Optimizing runtime reconfiguration decisions
In: Proceedings - IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2010, 2010, S. 39-46, 10.1109/EUC.2010.16

DynaCORE-dynamically reconfigurable coprocessor for network processors
In: Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, 2010, S. 335-354, 10.1007/978-90-481-3485-4_16

On the impact of buffer size on packet loss in adaptable network-on-chips for runtime reconfigurable system-on-chips
In: 2009 NORCHIP, 2009, 10.1109/NORCHP.2009.5397798

Adaptive communication architectures for runtime reconfigurable system-on-chips
In: Parallel Processing Letters, Vol. 18, 2008, Issue 2, S. 275-289, 10.1142/S0129626408003387

An application-oriented synthetic network traffic generator
In: Proceedings - 22nd European Conference on Modelling and Simulation, ECMS 2008, 2008, S. 299-305

Design and simulation of runtime reconfigurable systems
In: Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, 2008, S. 154-157, 10.1109/DDECS.2008.4538776

On the design parameters of runtime reconfigurable systems
In: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008, S. 683-686, 10.1109/FPL.2008.4630039

Performance analysis of bus-based interconnects for a run-time reconfigurable co-processor platform
In: Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2008, 2008, S. 200-205, 10.1109/PDP.2008.52

SPP1148 booth: Network processors
In: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008, S. 352, 10.1109/FPL.2008.4629960

WCET determination tool for embedded systems software
In: SIMUTools 2008 - 1st International ICST Conference on Simulation Tools and Techniques for Communications, Networks and Systems, 2008, 10.4108/ICST.SIMUTOOLS2008.3044

A lightweight framework for runtime reconfigurable system prototyping
In: Proceedings of the International Workshop on Rapid System Prototyping, 2007, S. 61-64, 10.1109/RSP.2007.7

Communication architectures for dynamically reconfigurable FPGA designs
In: Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM, 2007, 10.1109/IPDPS.2007.370364

Modelling tile-based run-time reconfigurable systems using SystemC
In: 21st European Conference on Modelling and Simulation: Simulations in United Europe, ECMS 2007, 2007, S. 509-514

On the design of a dynamically reconfigurable function-unit for error detection and correction
In: IFIP International Federation for Information Processing, Vol. 240, 2007, S. 283-297, 10.1007/978-0-387-73661-7_18

Teaching informatics students the secrets of hardware design
In: Proceedings - MSE 2007: 2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World, 2007, S. 31-32, 10.1109/MSE.2007.82

Exploring the capabilities of reconfigurable hardware for OFDM-based wlans
In: IFIP International Federation for Information Processing, Vol. 200, 2006, S. 149-164, 10.1007/0-387-33403-3_10

A dynamically reconfigurable packet-switched network-on-chip
In: Proceedings -Design, Automation and Test in Europe, DATE, Vol. 1, 2006

An adaptive system-on-chip for network applications
In: 20th International Parallel and Distributed Processing Symposium, IPDPS 2006, Vol. 2006, 2006, 10.1109/IPDPS.2006.1639445

Applying partial reconfiguration to networks-on-chips
In: Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, 2006, S. 155-160, 10.1109/FPL.2006.311208

Reconfigurable embedded systems: An application-oriented perspective on architectures and design techniques
In: Lecture Notes in Computer Science, Vol. 3553, 2005, S. 12-21

A dynamically reconfigurable function-unit for error detection and correction in mobile terminals
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 3203, 2004, S. 1090-1092

Design of a reconfigurable AES encryption/decryption engine for mobile terminals
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 2004, S. II545-II548

Reconfigurable platforms for ubiquitous computing
In: 2004 Computing Frontiers Conference, 2004, S. 377-389

On the Rapid Prototyping of Equalizers for OFDM Systems
In: Design Automation for Embedded Systems, Vol. 8, 2003, Issue 4, S. 283-295, 10.1023/B:DAEM.0000013063.88613.e0

Hardware evaluation of low power communication mechanisms for transport-triggered architectures
In: Proceedings of the International Workshop on Rapid System Prototyping, Vol. 2003-January, 2003, S. 141-147, 10.1109/IWRSP.2003.1207041

Reconfiguration requirements for high speed wireless communication systems
In: Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003, 2003, S. 118-125, 10.1109/FPT.2003.1275739

A framework for teaching (re)configurable architectures in student projects
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2438 LNCS, 2002, S. 444-451

On the rapid prototyping of equalizers for OFDM systems
In: Proceedings of the International Workshop on Rapid System Prototyping, Vol. 2002-January, 2002, S. 48-52, 10.1109/IWRSP.2002.1029737

Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture
In: Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001, 2001, S. 41-46, 10.1109/IWV.2001.923138

Efficient mapping of pre-synthesized IP-cores onto dynamically reconfigurable array architectures
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2147, 2001, S. 584-589

On the numerical accuracy of cordic-based frequency offset compensation in burst oriented OFDM systems
In: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Vol. 2, 2001, S. 1069-1072

Effiziente IP-basierte abbildungsverfahren für dynamisch rekonfigurierbare array-architekturen
In: ITG-Fachbericht, 2001, Issue 164, S. 315

An application-tailored dynamically reconfigurable hardware architecture for digital baseband processing
In: Proceedings - 13th Symposium on Integrated Circuits and Systems Design, 2000, S. 341-346, 10.1109/SBCCI.2000.876052

DReAM: A dynamically reconfigurable architecture for future mobile communication applications
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 1896, 2000, S. 312-321