Search & update optimization of a B + tree in a hardware aided semantic web database system
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Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs$Jan Moritz Joseph, ChristopherBlochwitz, Alberto García-Ortiz, Thilo Piontecka
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Semi-static operator graphs for accelerated query execution on FPGAs
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An FPGA-based prototyping framework for networks-on-Chip
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Contentious live-tracing as debugging approach on FPGAS
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Design method for asymmetric 3D interconnect architectures with high level models
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Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
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Hardware-accelerated radix-tree based string sorting for big data applications
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Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 3-6, 2017, Proceedings
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Runtime adaptive hybrid query engine based on FPGAs
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A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
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Accelerated join evaluation in Semantic Web databases by using FPGAs
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Adaptive allocation of default router paths in Network-on-Chips for latency reduction
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An architectural template for composing application specific datapaths at runtime
In: 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2016, 10.1109/ReConFig.2015.7393300

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases
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Hardware-accelerated pose estimation for embedded systems using vivado HLS
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Architecture of Computing Systems – ARCS 2016
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RAW 2014: Random number generators on FPGAS
In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 9, 2015, Issue 2, 10.1145/2807699

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
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Automated composition and execution of hardware-Accelerated operator graphs
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Hybrid FPGA approach for a B+ tree in a Semantic Web database system
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A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling
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Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation
In: 2014 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2014, 2014, 10.1109/ReConFig.2014.7032533

Influence of magnetic fields and X-radiation on ring oscillators in FPGAs
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Parallel and pipelined filter operator for hardware-accelerated operator graphs in semantic web databases
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Hardware-accelerated join processing in large Semantic Web databases with FPGAs
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Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems
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Register allocation for high-level synthesis of hardware accelerators targeting FPGAs
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An approach for performance estimation of hybrid systems with FPGAs and GPUs as coprocessors
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Linking formal description and simulation of runtime reconfigurable systems
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A concept of a trust management architecture to increase the robustness of nano age devices
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Latency reduction of selected data streams in network-on-chips for adaptive manycore systems
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Optimizing runtime reconfiguration decisions
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DynaCORE-dynamically reconfigurable coprocessor for network processors
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On the impact of buffer size on packet loss in adaptable network-on-chips for runtime reconfigurable system-on-chips
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Adaptive communication architectures for runtime reconfigurable system-on-chips
In: Parallel Processing Letters, Vol. 18, 2008, Issue 2, S. 275-289, 10.1142/S0129626408003387

An application-oriented synthetic network traffic generator
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Design and simulation of runtime reconfigurable systems
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On the design parameters of runtime reconfigurable systems
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Performance analysis of bus-based interconnects for a run-time reconfigurable co-processor platform
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SPP1148 booth: Network processors
In: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008, S. 352, 10.1109/FPL.2008.4629960

WCET determination tool for embedded systems software
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A lightweight framework for runtime reconfigurable system prototyping
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Communication architectures for dynamically reconfigurable FPGA designs
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Modelling tile-based run-time reconfigurable systems using SystemC
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On the design of a dynamically reconfigurable function-unit for error detection and correction
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Teaching informatics students the secrets of hardware design
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Exploring the capabilities of reconfigurable hardware for OFDM-based wlans
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A dynamically reconfigurable packet-switched network-on-chip
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An adaptive system-on-chip for network applications
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Applying partial reconfiguration to networks-on-chips
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Reconfigurable embedded systems: An application-oriented perspective on architectures and design techniques
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A dynamically reconfigurable function-unit for error detection and correction in mobile terminals
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 3203, 2004, S. 1090-1092

Design of a reconfigurable AES encryption/decryption engine for mobile terminals
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 2004, S. II545-II548

Reconfigurable platforms for ubiquitous computing
In: 2004 Computing Frontiers Conference, 2004, S. 377-389

On the Rapid Prototyping of Equalizers for OFDM Systems
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Hardware evaluation of low power communication mechanisms for transport-triggered architectures
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Reconfiguration requirements for high speed wireless communication systems
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A framework for teaching (re)configurable architectures in student projects
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On the rapid prototyping of equalizers for OFDM systems
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Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture
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Efficient mapping of pre-synthesized IP-cores onto dynamically reconfigurable array architectures
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On the numerical accuracy of cordic-based frequency offset compensation in burst oriented OFDM systems
In: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Vol. 2, 2001, S. 1069-1072

Effiziente IP-basierte abbildungsverfahren für dynamisch rekonfigurierbare array-architekturen
In: ITG-Fachbericht, 2001, Issue 164, S. 315

An application-tailored dynamically reconfigurable hardware architecture for digital baseband processing
In: Proceedings - 13th Symposium on Integrated Circuits and Systems Design, 2000, S. 341-346, 10.1109/SBCCI.2000.876052

DReAM: A dynamically reconfigurable architecture for future mobile communication applications
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